The present invention relates to a semiconductor device and a semiconductor module which are thin and can be mounted at high density, and particularly to a semiconductor device and a semiconductor module in which heat cycle resistance can be improved and short circuits can be prevented from occurring between solder bumps.
FIG. 10 is a plan view showing the configuration of a semiconductor device of the conventional art which is disclosed in, for example, Unexamined Japanese Patent Application No. Hei 9-321218, and FIG. 11 is a side view of FIG. 10. Referring to FIGS. 10 and 11, IC package mounting lands 13 are arranged on upper and lower faces of a substrate 11. Furthermore, external connection lands 14 serving as external connection terminals are arranged on the upper and lower faces of the substrate 11 and outside the IC package mounting lands 13, so as to respectively correspond to the IC package mounting lands 13. In the external connection lands 14 and the IC package mounting lands 13, each corresponding pair of lands is electrically connected via a wiring 15 on the substrate 11. With respect to the external connection lands 14, each vertically corresponding pair of lands which are respectively disposed on the upper and lower faces of the substrate 11 are electrically connected to each other via, for example, a conductor in a through hole.
In one of the faces of the substrate 11 (in FIG. 11, the lower face), solder bumps 16 for external connection are located on the external connection lands 14, respectively. An IC package 17 comprises a package body 18, and straight leads 19 which project straightly and laterally from the right and left side faces of the body 18. The straight leads 19 are fixed onto the corresponding IC package mounting lands 13 and electrically connected thereto, and supported by the substrate 11. In this way, a semiconductor device 24 is configured.
The semiconductor device 24 is configured in the following procedure. First, an IC package 17 is positioned on the upper face of the substrate 11, and the straight leads 19 are soldered to the IC package mounting lands 13 using a reflow technique. Next, the substrate 11 is turned over. Thereafter, another IC package 17 is similarly soldered to the lower face of the substrate 11, and the solder bumps 16 are soldered to the external connection lands 14.
Next, the configuration of a semiconductor module will be described. FIG. 12 is a side view showing the configuration of a semiconductor module of the conventional art in which the semiconductor device of FIGS. 10 and 11 is soldered to a mother board. Referring to FIG. 12, lands 21 for mounting the semiconductor device 24 are disposed on the upper face of a mother board 20. Usually, there are larger dimensional margins around the lands 21 as compared with the case of the external connection lands 14, and hence the lands 21 are larger in sectional area than the external connection lands 14. The semiconductor device 24 is fixed onto the lands 21 via the solder bumps 16 so as to accomplish electrical connections. In this way, a semiconductor module 25 is configured.
The semiconductor module 25 is connected and fixed to the mother board in the following procedure. First, the semiconductor device 24 is positioned on the upper face of the mother board 20. At this time, solder paste is previously supplied to portions where the solder bumps 16 are to abut against the lands 21, respectively. Thereafter, the solder paste and the solder bumps 16 are melted, so that the substrate 11 and the mother board 20 are connected and fixed to each other.
Next, in order to check the thermal fatigue life of the semiconductor module 25, a temperature cycle test in which a temperature change between, for example, xe2x88x9240 and 125xc2x0 C. is imposed every 30 minutes is performed on the completed semiconductor module 25. FIG. 13 is a diagram showing a section where the semiconductor devices 24 and the mother board 20 which have undergone the temperature cyclic test are bonded to each other via the solder bumps 16 and the lands 21.
Referring to FIG. 13, when the semiconductor devices 24 are to be soldered to the mother board 20, the semiconductor device 24 which is first bonded is subjected to the reflow process while being downward directed, and therefore the solder bumps 16 are elongated by the weight of the semiconductor device 24. The semiconductor device 24 which is next bonded is subjected to the reflow process while being upward directed, and therefore the solder bumps 16 are compressed by their own weight.
This phenomenon causes a short circuit between the solder bumps 16 as described below. When solder paste is applied to the connection lands 21 on the upper and lower faces of the mother board 20 by using a solder print mask (not shown) having openings of the strictly same dimension, and the solder bumps 16 are bonded to the lands, the upper solder bumps 16 are pressed to expand together with the solder paste beyond the predetermined bonding portions as shown in FIG. 13. As a result, when the reflow process is performed, a short circuit may occur between adjacent solder bumps 16.
During the reflow process, the lower solder bumps 16 are elongated by the weight of the semiconductor device 24 and the sectional area of the bonding portions is reduced. As a result, when a temperature cyclic test is thereafter a performed, a crack due to thermal fatigue is formed in the solder bonding portions, thereby causing the portions to be broken. Such breakage due to thermal fatigue easily occurs in bonding interfaces between the external connection lands 14 which are smaller in sectional area than the lands 21, and the solder bumps 16. This is related to the moment of inertia of the area of the bonding portion section in each bonding interface, i.e., the diameter of the bonding portion section in each bonding interface. Consequently, breakage may occur in a part of a small sectional area of the bonding portion section.
On the semiconductor module 25, mounted are elements which have different coefficients of thermal expansion, namely, the mother board 20, the substrate 11, the IC packages 17, and circuit components. Therefore, temperature changes occurring during the operation of a final product or a temperature cyclic test causes the solder bonding portions to be thermally deformed. The degree of the thermal deformation is proportional to the difference of the coefficients of thermal expansion, the distance between the solder bonding portions, and the temperature difference. Therefore, the greatest thermal deformation is produced in the solder bonding portions in the external connection lands 14 corresponding to the IC package mounting lands 13 which are respectively positioned at the ends and have the longest length of solder fixation. When breakage occurs, the end solder bonding portions are broken early.
In order to prevent cracks due to thermal fatigue from being produced in the solder bonding portions to break the portions, or breakage due to thermal deformation from occurring in the solder bonding portions, it may be contemplated that the diameter of the solder bumps 16 is increased. The reason why the diameter of the solder bumps 16 is increased will be described. Each solder bump 16 is approximated by a columnar model having a diameter D, and a load which can be held is estimated. When a load W is applied to the center line of the column, a stress "sgr"=4xc3x97W/(xcfx80xc3x97Dxc3x97D) is produced in any section over the whole length of the column. When the allowable stress of the solder at the temperature of the reflow process, for example, about 200xc2x0 C. is indicated by "sgr"a, the allowable load W of the solder columns (the solder bumps 16) can be obtained as W="sgr"axc3x97xcfx80xc3x97Dxc3x97D/4. From this expression, it will be seen that the load W which can be held by a single solder column is proportional to the square of the diameter D of a bonding interface between each of the solder bumps 16 and the land 14 or 21. In order to increase the supportable load, therefore, the diameter D of the solder bumps 16 must be enlarged.
In the semiconductor device and the semiconductor module of the conventional art which have been described above, the external connection lands 14 corresponding to the IC package mounting lands 13 which are connected to the straight leads 19 of the semiconductor device 24 are disposed in one row and with a regular pitch. On the other hand, the diameter of the solder bumps 16 which are connected to the external connection lands 14 must be held to a minimum value in order to ensure the insulation distance, thereby preventing a short circuit from occurring between the solder bumps 16. Therefore, the diameter is restricted by the pitch and cannot be enlarged. Even when the external connection lands 14 and dummy lands 14a are arranged as shown in FIGS. 14A and 14B, the diameter of the solder bumps 16 is similarly restricted by the pitches of the lands and cannot be enlarged.
As described above, the diameter of the solder bumps 16 cannot be enlarged. Consequently, there arise problems in that breakage due to thermal fatigue cannot be prevented from being produced in the solder bonding portions between the solder bumps 16 and the lands 14 and 21, and also that breakage due to thermal deformation cannot be prevented from occurring in the solder bonding portions.
When the diameter of the solder bumps 16 is enlarged in order to prevent the solder bonding portions from being broken, there arises another problem in that a short circuit occurs between the solder bumps 16.
In order to prevent the solder bonding portions which, during the reflow process, are elongated by the weight of the downward-directed semiconductor device 24 mounted on the semiconductor module 25 to reduce the sectional areas of the bonding portions, from being cracked by thermal fatigue and broken, the package body 18 and the mother board 20 may be bonded together by an adhesive agent. However, this countermeasure has problems in that a bonding step is additionally required, and that the production cost is high.
The invention has been conducted in order to solve the above-discussed problems. It is an object of the invention to provide a semiconductor device and a semiconductor module in which breakage due to thermal fatigue is prevented from occurring in solder bonding portions between solder bumps and lands, or breakage due to thermal deformation is prevented from occurring in the solder bonding portions.
It is another object of the invention to provide a semiconductor device and a semiconductor module in which, even when the diameter of semiconductor bumps is enlarged so as to prevent solder bonding portions from being broken, it is possible to prevent a short circuit from occurring between the solder bumps.
It is a further object of the invention to provide a semiconductor device and a semiconductor module which can eliminate a production step of bonding a package body to a mother board which is to be conducted in order to prevent solder bonding portions from being broken.
In the semiconductor device of the embodiment, the device comprises: at least two substrates each of which has upper and lower faces, and which are placed so that end faces of the substrates are opposed to each other, thereby forming a space between the end faces; and a pair of integrated circuit packages each of which has a package body and plural leads that are drawn out from the package body, the packages being respectively disposed in upper and lower sides of the space, plural external connection terminals which are disposed on extended lines of the leads of the integrated circuit packages, and which are correspondingly connected to the plural leads are formed on the upper and lower faces of the substrates, the external connection terminals are configured by: first-group external connection terminals which are arranged on a side of the integrated circuit packages; and second-group external connection terminals which are arranged outside the first-group external connection terminals, the first-group external connection terminals and the second-group external connection terminals are arranged in a staggered pattern, and external connection bumps which are connected to the external connection terminals are disposed on at least one of the upper and lower faces of the substrates.
The device is configured so that an interval between adjacent terminals in first-group external connection terminals or second-group external connection terminals is twice an interval between corresponding leads of the integrated circuit packages.
The device is configured so that the external connection bumps have a diameter which is larger than a dimension of an interval between corresponding leads of the integrated circuit packages.
The device is configured so that dummy external connection terminals which are not connected to the integrated circuit packages are disposed on the substrates and outside end ones of the first-group external connection terminals and the second-group external connection terminals.
In a semiconductor module in which a semiconductor device is disposed on a mother board where a functional circuit is configured, the semiconductor device comprises: at least two substrates each of which has upper and lower faces, and which are placed so that end faces of the substrates are opposed to each other, thereby forming a space between the end faces; and a pair of integrated circuit packages each of which has a package body and plural leads that are drawn out from the package body, the packages being respectively disposed in upper and lower sides of the space, plural external connection terminals which are disposed on extended lines of the leads of the integrated circuit packages, and which are correspondingly connected to the plural leads are formed on the upper and lower faces of the substrates, the external connection terminals are configured by: first-group external connection terminals which are arranged on a side of the integrated circuit packages; and second-group external connection terminals which are arranged outside the first-group external connection terminals, the first-group external connection terminals and the second-group external connection terminals are arranged in a staggered pattern, external connection bumps which are connected to the external connection terminals are disposed on at least one of the upper and lower faces of the substrates, and the external connection bumps of the semiconductor device are connected to the mother board.
The module is configured so that one set of the external connection bumps is connected to first connection lands constituting the external connection terminals, another set of the external connection bumps is connected to second connection lands formed on the mother board, and a diameter of the first connection lands is equal to a diameter of the second connection lands.
The module is configured so that the semiconductor device is disposed on each of both the upper and lower faces of the mother board, the external connection bumps disposed on the semiconductor devices are connected to the mother board, and first positions where the external connection bumps on a side of the upper face are connected to the mother board are shifted from second positions where the external connection bumps on a side of the lower face are connected to the mother board.
The module is configured so that dummy external connection terminals which are not connected to the integrated circuit packages are disposed on the substrates and outside end ones of the first-group external connection terminals and the second-group external connection terminals, and external connection bumps which are connected to the dummy external connection terminals are disposed on at least one of the upper and lower faces of the substrates.